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EL8171, EL8172
Data Sheet March 9, 2006 FN6293.1
Micropower, Single Supply, Rail-to-Rail Input-Output Instrumentation Amplifiers
The EL8171 and EL8172 are micropower instrumentation amplifiers optimized for operation at 2.9V to 5V single supplies. Inputs and outputs can operate rail-to-rail. As with all instrumentation amplifiers, a pair of inputs provide very high common-mode rejection and are completely independent from a pair of feedback terminals. The feedback terminals allow zero input to be translated to any output offset, including ground. A feedback divider controls the overall gain of the amplifier. The EL8172 is compensated for a gain of 100 or more, and the EL8171 is compensated for a gain of 10 or more. The EL8171 and EL8172 have PMOS input devices that provide sub-nA input bias currents. The amplifiers can be operated from one lithium cell or two Ni-Cd batteries. The EL8171 and EL8172 input range goes from below ground to slightly above positive rail. The output stage swings completely to ground or positive supply - no pull-up or pull-down resistors are needed.
Features
* 78A maximum supply current * Maximum input offset voltage - 300V (EL8172) - 1000V (EL8171) * 200pA maximum input bias current * 3V/C offset voltage drift * 450kHz -3dB bandwidth (G = 10) * 170kHz -3dB bandwidth (G = 100) * 0.5V/s slew rate * Single supply operation - Input voltage range is rail-to-rail - Output swings rail-to-rail * Output sources and sinks 29mA load current * 0.2% gain accuracy * Pb-free plus anneal available (RoHS compliant)
Pinout
EL8171, EL8172 (8 LD SO) TOP VIEW
ENABLE 1 IN- 2 IN+ 3 VS- 4
+ + -
Applications
* Battery- or solar-powered systems * Strain gauges * Current monitors
8 FB+ 7 VS+ 6 OUT 5 FB-
* Thermocouple amplifiers
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL8171, EL8172 Ordering Information
PART NUMBER EL8171IS EL8171IS-T7 EL8171IS-T13 EL8171ISZ (See Note) EL8171ISZ-T7 (See Note) EL8171ISZ-T13 (See Note) PART MARKING 8171IS 8171IS 8171IS 8171ISZ 8171ISZ 8171ISZ TAPE & REEL 7" 13" 7" 13" PACKAGE 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO (Pb-free) 8 Ld SO (Pb-free) 8 Ld SO (Pb-free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 PART NUMBER EL8172IS EL8172IS-T7 EL8172IS-T13 EL8172ISZ (See Note) EL8172ISZ-T7 (See Note) EL8172ISZ-T13 (See Note) PART MARKING 8172IS 8172IS 8172IS 8172ISZ 8172ISZ 8172ISZ TAPE & REEL 7" 13" 7" 13" PACKAGE 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO (Pb-free) 8 Ld SO (Pb-free) 8 Ld SO (Pb-free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Description
EL8171/EL8172 1 2 3 5 8 PIN NAME ENABLE ININ+ FBFB+ PIN FUNCTION Active Low. When pulled up above 2V, the in-amp conserves 3A disabled supply current and the output is in a high impedance state. An internal pull down defines the ENABLE low when left floating. Inverting (IN-) and non-inverting (IN+) high impedance input terminals. The input terminals are equivalent to the gate of PMOS transistor. High impedance feedback terminals. The feedback terminals have a very similar equivalent circuit as the input terminals. The negative feedback (FB-) pin connects to an external resistive network to set the gain of the in-amp. The positive feedback (FB+) pin can be used to shift the DC level of the output or as an output offset. Positive supply terminal. Negative supply terminal. Output Voltage.
7 4 6
VS+ VSVOUT
2
FN6293.1 March 9, 2006
EL8171, EL8172
Absolute Maximum Ratings (TA = 25C)
Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V VEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V to VS+ + 0.5V ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER VOS
VS+ = +5V, VS- = GND, VCM = 1/2VS+ TA = 25C, unless otherwise specified. CONDITIONS EL8171 EL8172 MIN TYP 400 150 3 10 10 EL8171 EL8172 f = 0.1Hz to 10Hz 10 4 fo = 1kHz 200 70 25 Guaranteed by CMRR test EL8172, VCM = 0V to +5V EL8171, VCM = 0V to +5V 0 80 80 80 70 -1.5 -0.8 0 108 104 104 90 +0.3 +0.2 4 0.13 4.990 4.75 0.3 4.996 4.88 0.5 450 210 66 33 172 70 25 12 0.7 +1.5 +0.8 10 0.25 5 200 200 MAX 1000 300 UNIT V V V/C pA pA VP-P VP-P nV/Hz nV/Hz G V dB dB dB dB % % mV V V V V/s kHz kHz kHz kHz kHz kHz kHz kHz
DESCRIPTION Input Offset Voltage
TCVOS
Input Offset Voltage Temperature Coefficient Input Offset Current Input Bias Current Input Noise Voltage
Temperature = -40C to 85C
IOS IB eN
Input Noise Voltage Density
EL8171 EL8172
RIN VIN CMRR
Input Resistance Input Voltage Range Common Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
EL8172, VS = 2.4V to 5V EL8171, VS = 2.4V to 5V
EG
Gain Error
EL8172, RL = 100k to 2.5V EL8171, RL = 100k to 2.5V
VOUT
Maximum Voltage Swing
Output low, 100k to 2.5V Output low, 1k to 2.5V Output high, 100k to 2.5V Output high, 1k to GND
SR -3dB BW
Slew Rate -3dB Bandwidth
RL = 1k to GND EL8171 Gain = 10V/V Gain = 20 Gain = 50 Gain = 100 EL8172 Gain = 100 Gain = 200 Gain = 500 Gain = 1000
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FN6293.1 March 9, 2006
EL8171, EL8172
Electrical Specifications
PARAMETER IS,EN IS,DIS VENH VENL VS IO VS+ = +5V, VS- = GND, VCM = 1/2VS+ TA = 25C, unless otherwise specified. (Continued) CONDITIONS MIN 40 EN = VS+ 1.5 2 0.8 2.2 VS = 5V VS = 2.9V 18 4 29 7.5 2.4 TYP 60 2.9 MAX 78 5 UNIT A A V V V mA mA
DESCRIPTION Supply Current, Enabled Supply Current, Disabled Enable Pin for Shut-down Enable Pin for Power-on Minimum Supply Voltage Output Current into 10 to VS/2
Typical Performance Curves
G=100 40 G=50 30 G=20 G=10 20 G=5 10 Vs=5V 0 1 10 100 1K 10K 100K 1M
FREQUENCY (Hz)
70
G=2000 G=1000 G=500 G=200 G=100
60
GAIN (dB)
GAIN (dB)
50
40
G=50
30 Vs=5V 20 1 10 100 1K 10K 100K 1M
FREQUENCY (Hz)
FIGURE 1. EL8171 FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FIGURE 2. EL8172 FREQUENCY RESPONSE vs CLOSED LOOP GAIN
25 VS=2.5V 20
MAGNITUDE (dB)
45 40 35 30 25 20 AV=100 15 R =10k L 10 CL=10pF RF/RG=99.02 5 RF=221k RG=2.23k 0 100 1k VS=1V VS=1.25V VS=2.5V
VS=1.25V
GAIN (dB)
15 10 A =10 V RL=10k CL=10pF 5 R /R =9.08 FG RF=178k RG=19.6k 0 100 1k
VS=1V
10k
100k
1M
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. EL8171 FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 4. EL8172 FREQUENCY RESPONSE vs SUPPLY VOLTAGE
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FN6293.1 March 9, 2006
EL8171, EL8172 Typical Performance Curves (Continued)
30 25
MAGNITUDE (dB)
50 CL=100pF
MAGNITUDE (dB)
CL=47pF 20 15 A =10 10 VV=5V S RL=10k RF/RG=9.08 5 RF=178k RG=19.6k 0 100 1k
45 CL=1000pF 40 CL=820pF 35 A =100 V VS=5V RL=10k 30 R /R =99.02 FG RF=221k RG=2.23k 25 100 1k
CL=2200pF
CL=27pF
CL=390pF
10k
100k
1M
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. EL8171 FREQUENCY RESPONSE vs CLOAD
FIGURE 6. EL8172 FREQUENCY RESPONSE vs CLOAD
4 AVERAGE INPUT BIAS CURRENT (pA)
25C 25C
2
AVERAGE INPUT BIAS CURRENT (pA)
4
-45C -45C
2
0
0
Vs=2.9V
-2
Vs=3.3V Vs=5V
-2
Vs=2.9V
Vs=3.3V Vs=5V
-4 -0.5
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 COMMON-MODE INPUT VOLTAGE (V)
5
5.5
-4 -0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 7. EL8171 AND EL8172 AVERAGE INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE @ 25C
FIGURE 8. EL8171 AND EL8172 AVERAGE INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE @ -45C
100 AVERAGE INPUT BIAS CURRENT (pA) INPUT OFFSET CURRENT (pA)
85C 85C
10 Vs=5V 5
50 Vs=5V 0
0
-50
-5
Vs=2.9V
Vs=3.3V
-100 -0.5
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 COMMON-MODE INPUT VOLTAGE (V)
5
5.5
-10 -0.5
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 COMMON-MODE INPUT VOLTAGE (V)
5
5.5
FIGURE 9. EL8171 AND EL8172 AVERAGE INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE @ 85C
FIGURE 10. EL8171 AND EL8172 INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE
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FN6293.1 March 9, 2006
EL8171, EL8172 Typical Performance Curves (Continued)
600 INPUT OFFSET VOLTAGE (uV) 500 400 300 200 100 0 -0.5 Vs=2.9V Vs=5.0V
INPUT OFFSET VOLTAGE (uV)
25C 25C
200
25C 25C
100
Vs=5V
0
Vs=2.9V Vs=3.3V
Vs=3.3V
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-200 -0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 11. EL8171 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ 25C
FIGURE 12. EL8172 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ 25C
600 500 400 300 200 100 0 -0.5 Vs=2.9V Vs=3.3V
-45C -45C
100 INPUT OFFSET VOLTAGE (uV)
-45C -45C
INPUT OFFSET VOLTAGE (uV)
0
Vs=5.0V
Vs=5V
-100
-200
Vs=2.9V
Vs=3.3V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-300 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 13. EL8171 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ -45C
FIGURE 14. EL8172 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ -45C
800 INPUT OFFSET VOLTAGE (uV) 700 600 500 400 300 200 -0.5 Vs=2.9V Vs=3.3V Vs=5.0V INPUT OFFSET VOLTAGE (uV)
85C 85C
500
85C 85C
400
Vs=5V
300
200
Vs=2.9V
Vs=3.3V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
100 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 15. EL8171 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ 85C
FIGURE 16. EL8172 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ 85C
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FN6293.1 March 9, 2006
EL8171, EL8172 Typical Performance Curves (Continued)
120 110 100 CMRR (dB) CMRR (dB) 90 80 70 60 50 40 1 10 100 1K 10K 100K 1M FREQUENCY (Hz) GAIN=10 GAIN=100 120 110 100 90 80 70 60 50 40 1 10 100 1K 10K 100K 1M FREQUENCY (Hz) GAIN=1000 GAIN=100
FIGURE 17. EL8171 CMRR vs FREQUENCY
FIGURE 18. EL8172 CMRR vs FREQUENCY
100
120
PSRR+ PSRR (dB) PSRR (dB) 80
100
PSRR+
80
PSRR60
PSRR-
60
40
1
10
100
1K
10K
100K
1M
40
1
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. EL8171 PSRR vs FREQUENCY
FIGURE 20. EL8172 PSRR vs FREQUENCY
1K
INPUT VOLTAGE NOISE (nV/Hz) INPUT VOLTAGE NOISE (nV/Hz)
1K 1000
eN@ 1kHz = 200nV/Hz
eN@ 1kHz = 70nV/Hz
100
100 10 100 1K 10K FREQUENCY (Hz)
10 10 100 1K 1,000 10K 10,000 FREQUENCY (Hz)
FIGURE 21. EL8171 VOLTAGE NOISE SPECTRAL DENSITY
FIGURE 22. EL8172 VOLTAGE NOISE SPECTRAL DENSITY
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FN6293.1 March 9, 2006
EL8171, EL8172 Typical Performance Curves (Continued)
5uV/DIV
1uV/DIV
1s/DIV
1s/DIV
FIGURE 23. EL8171 0.1Hz to 10Hz INPUT VOLTAGE NOISE (GAIN = 10)
FIGURE 24. EL8172 0.1Hz to 10Hz INPUT VOLTAGE NOISE (GAIN = 100)
70 60
SUPPLY CURRENT (A)
50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
FIGURE 25. EL8171 AND EL8172 SUPPLY CURRENT vs SUPPLY VOLTAGE
1.4
POWER DISSIPATION (W)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1 0.9
POWER DISSIPATION (W)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1.2 1 909mW 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150
SO 11 8 0 C/ W
0.8 0.7 625mW 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150
JA
JA =
=1
60
SO 8 C /W
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN6293.1 March 9, 2006
EL8171, EL8172 Description of Operation and Application Information
Product Description
The EL8171 and EL8172 are micropower instrumentation amplifiers (in-amps) which deliver rail-to-rail input amplification and rail-to-rail output swing on a single 2.4V to 5V supply. The EL8171 and EL8172 also deliver excellent DC and AC specifications while consuming only 60A typical supply current. Because EL8171 and EL8172 provide an independent pair of feedback terminals to set the gain and to adjust the output level, these in-amps achieve high commonmode rejection ratio regardless of the tolerance of the gain setting resistors. The EL8171 is internally compensated for a minimum closed loop gain of 10 or greater, well suited for moderate to high gains. For higher gains, the EL8172 is internally compensated for a minimum gain of 100. An ENABLE pin is used to reduce power consumption, typically 2.9A, while the instrumentation amplifier is disabled. obsession of the EL8171 and EL8172 in-amp is to maintain the differential voltage across FB+ and FB- equal to IN+ and IN-; (FB+ - FB-) = (IN+ - IN-). Consequently, the transfer function can be derived. The gain of the EL8171 and EL8172 is set by two external resistors, the feedback resistor RF, and the gain resistor RG.
2.9V to 5V 7 VIN/2 2 IN+ 3 IN8 FB+ 5 FB+ + 4 1 VS+ EN 6 VOUT EN_BAR
VIN/2 VCM
EL8171/2 VS-
RG
RF
Input Protection
All input and feedback terminals of the EL8171 and EL8172 have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode drop beyond the supply rails. If overdriving the inputs is necessary, the external input current must never exceed 5mA. External series resistor may be used as a protection to limit excessive external voltage and current from damaging the inputs.
FIGURE 28. CIRCUIT 1 - GAIN IS BY EXTERNAL RESISTORS RF AND RG RF VOUT = 1 + ------- VIN R G
Input Stage and Input Voltage Range
The input terminals (IN+ and IN-) of the EL8171 and EL8172 are single differential pair P-MOSFET devices aided by an Input Range Enhancement Circuit to increase the headroom of operation of the common-mode input voltage. The feedback terminals (FB+ and FB-) also have a similar topology. As a result, the input common-mode voltage range of both the EL8171 and EL8172 is rail-to-rail. These in-amps are able to handle input voltages that are at or slightly beyond the supply and ground making these in-amps well suited for single 5V or 3.3V low voltage supply systems. There is no need then to move the common-mode input of the in-amps to achieve symmetrical input voltage.
In Figure 28, the FB+ pin and one end of resistor RG are connected to GND. With this configuration, the above gain equation is only true for a positive swing in VIN; negative input swings will be ignored and the output will be at ground.
Reference Connection
Unlike a three-opamp instrumentation amplifier, a finite series resistance seen at the REF terminal does not degrade the EL8171 and EL8172's high CMRR performance eliminating the need for an additional external buffer amplifier. Circuit 2 (Figure 29) uses the FB+ pin to provide a high impedance REF terminal.
2.9V to 5V 7 VIN/2 2 IN+ 3 IN8 FB+ 5 FB+ + 4 1 VS+ EN 6 VOUT EN_BAR
VIN/2 VCM 2.9V to 5V R1 REF R2 RG
Output Stage and Output Voltage Range
A pair of complementary MOSFET devices drives the output VOUT to within a few mV of the supply rails. At a 100k load, the PMOS sources current and pulls the output up to 4mV below the positive supply, while the NMOS sinks current and pulls the output down to 4mV above the negative supply, or ground in the case of a single supply operation. The current sinking and sourcing capability of the EL8171 and EL8172 are internally limited to 29mA.
EL8171/2 VS-
RF
Gain Setting
VIN, the potential difference across IN+ and IN-, is replicated (less the input offset voltage) across FB+ and FB-. The 9
FIGURE 29. CIRCUIT 2 - GAIN SETTING AND REFERENCE CONNECTION RF RF VOUT = 1 + ------- ( VIN ) + 1 + ------- ( VREF ) R G R G
FN6293.1 March 9, 2006
EL8171, EL8172
The FB+ pin is used as a REF terminal to center or to adjust the output. Because the FB+ pin is a high impedance input, an economical resistor divider can be used to set the voltage at the REF terminal without degrading or affecting the CMRR performance. Any voltage applied to the REF terminal will shift VOUT by VREF times the closed loop gain, which is set by resistors RF and RG. See Circuit 2 (Figure 29). The FB+ pin can also be connected to the other end of resistor, RG. See Circuit 3 (Figure 30). Keeping the basic concept that the EL8171 and EL8172 in-amps maintain constant differential voltage across the input terminals and feedback terminals (IN+ - IN- = FB+ - FB-), the transfer function of Circuit 3 can be derived.
2.9V to 5V 7 VIN/2 2 IN+ 3 IN8 FB+ 5 FB+ + 4 1 VS+ EN 6 VOUT EN_BAR
error due to the tolerance of the resistors used. The resulting non-ideal transfer function effectively becomes:
RF VOUT = 1 + ------- x [ 1 - ( E RG + E RF + E G ) ] x VIN R G
Where:
ERG = Tolerance of RG ERF = Tolerance of RF EG = Gain Error of the EL8171 or EL8172
The term [1-(ERG +ERF +EG)] is the deviation from the theoretical gain. Thus, (ERG +ERF +EG) is the total gain error. For example, if 1% resistors are used for the EL8171, the total gain error would be:
= ( E RG + E RF + E G ( typical ) ) = ( 0.01 + 0.01 + 0.003 ) = 2.3%
VIN/2 VCM
EL8171/2 VS-
Disable/Power-Down
The EL8171 and EL8172 can be powered down reducing the supply current to typically 2.9A. When disabled, the output is in a high impedance state. The active low ENABLE bar pin has an internal pull down and hence can be left floating and the in-amp enabled by default. When the ENABLE bar is connected to an external logic, the in-amp will power down when ENABLE bar is pulled above 2V, and will power on when ENABLE bar is pulled below 0.8V.
RG VREF
RF
FIGURE 30. CIRCUIT 3 - REFERENCE CONNECTION WITH AN AVAILABLE VREF RF VOUT = 1 + ------- ( VIN ) + ( VREF ) R G
A finite resistance Rs in series with the VREF source, adds an output offset of VIN*(RS/RG). As the series resistance Rs approaches zero, the gain equation is simplified to the above equation for Circuit 3. VOUT is simply shifted by an amount VREF.
External Resistor Mismatches
Because of the independent pair of feedback terminals provided by the EL8171 and EL8172, the CMRR is not degraded by any resistor mismatches. Hence, unlike a three opamp and especially a two opamp in-amp, the EL8171 and EL8172 reduce the cost of external components by allowing the use of 1% or more tolerance resistors without sacrificing CMRR performance. The EL8171 and EL8172 CMRR will be 108dB regardless of the tolerance of the resistors used.
Gain Error and Accuracy
The EL8172 has a Gain Error, EG, of 0.2% typical. The EL8171 has an EG of 0.3% typical. The gain error indicated in the electrical specifications table is the inherent gain error of the EL8171 and EL8172 and does not include the gain error contributed by the resistors. There is an additional gain
10
FN6293.1 March 9, 2006
EL8171, EL8172 Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6293.1 March 9, 2006

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